完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLin, Chia-Pinen_US
dc.contributor.authorTsui, Bing-Yueen_US
dc.date.accessioned2014-12-08T15:25:08Z-
dc.date.available2014-12-08T15:25:08Z-
dc.date.issued2006en_US
dc.identifier.isbn1-4244-0181-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/17508-
dc.description.abstractThe hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices.en_US
dc.language.isoen_USen_US
dc.titleImpact of back gate bias on hot-carrier effects of n-channel tri-gate FETs (TGFETs)en_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Proceedings of Technical Papersen_US
dc.citation.spage82en_US
dc.citation.epage83en_US
dc.contributor.department電機學院zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000239791300029-
顯示於類別:會議論文