完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yen, CC | en_US |
dc.contributor.author | Jou, JY | en_US |
dc.date.accessioned | 2014-12-08T15:25:10Z | - |
dc.date.available | 2014-12-08T15:25:10Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-9571-9 | en_US |
dc.identifier.issn | 1552-6674 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17557 | - |
dc.description.abstract | Diagnosing counter examples with error traces has acted as one of the most critical steps in functional verification. Unfortunately, error traces are normally very lengthy such that designers need to spend considerable effort to understand them. To alleviate designers' burden for debugging, we present a SAT-based algorithm for reducing the lengths of error traces. The algorithm performs the paradigm of binary search algorithm to halve the search space recursively. Furthermore, it applies a novel theorem to guarantee to gain the shortest lengths for the error traces. Experimental results demonstrate that our approach greatly surpasses previous work and indeed has the optimum solutions. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An optimum algorithm for compacting error traces for efficient functional debugging | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | HLDVT'05: TENTH ANNUAL IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | en_US |
dc.citation.spage | 177 | en_US |
dc.citation.epage | 183 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000235258100022 | - |
顯示於類別: | 會議論文 |