完整後設資料紀錄
DC 欄位語言
dc.contributor.authorYen, CCen_US
dc.contributor.authorJou, JYen_US
dc.date.accessioned2014-12-08T15:25:10Z-
dc.date.available2014-12-08T15:25:10Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-9571-9en_US
dc.identifier.issn1552-6674en_US
dc.identifier.urihttp://hdl.handle.net/11536/17557-
dc.description.abstractDiagnosing counter examples with error traces has acted as one of the most critical steps in functional verification. Unfortunately, error traces are normally very lengthy such that designers need to spend considerable effort to understand them. To alleviate designers' burden for debugging, we present a SAT-based algorithm for reducing the lengths of error traces. The algorithm performs the paradigm of binary search algorithm to halve the search space recursively. Furthermore, it applies a novel theorem to guarantee to gain the shortest lengths for the error traces. Experimental results demonstrate that our approach greatly surpasses previous work and indeed has the optimum solutions.en_US
dc.language.isoen_USen_US
dc.titleAn optimum algorithm for compacting error traces for efficient functional debuggingen_US
dc.typeProceedings Paperen_US
dc.identifier.journalHLDVT'05: TENTH ANNUAL IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGSen_US
dc.citation.spage177en_US
dc.citation.epage183en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000235258100022-
顯示於類別:會議論文