標題: Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
作者: Jiang, Tai-Ying
Liu, Chien-Nan Jimmy
Jou, Jing-Yang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Error diagnosis;hardware description language (HDL);HDL code debugging;verification
公開日期: 1-二月-2009
摘要: When hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true design errors among the candidates in the set may still consume much valuable time. A debugging priority method [21] was proposed to speed up the error-searching process in the derived error candidate set. The idea is to display error candidates in an order that corresponds to an individual's degree of suspicion. With this method, error candidates are placed in a rank order based on their probability of being an error. The more likely an error candidate is, a design error (or a bug), the higher the rank order that it has. With the displayed rank order, circuit designers should find design errors quicker than with blind searching when searching for design errors among all the derived candidates. However, the currently used confidence score (CS) for deriving the debugging priority has some flaws in estimating the likelihood of correctness of error candidates due to the masking error situation. This reduces the degree of accuracy in establishing a debugging priority. Therefore, the objective of this work is to develop a new probabilistic confidence score (PCS) that takes the masking error situation into consideration in order to provide a more reliable and accurate debugging priority. The experimental results show that our proposed PCS achieves better results in estimating the likelihood of correctness and can indeed suggest a debugging priority with better accuracy, as compared to the CS.
URI: http://dx.doi.org/10.1109/TCAD.2008.2009163
http://hdl.handle.net/11536/7684
ISSN: 0278-0070
DOI: 10.1109/TCAD.2008.2009163
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 28
Issue: 2
起始頁: 272
結束頁: 284
顯示於類別:期刊論文


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