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dc.contributor.authorCheng, CCen_US
dc.contributor.authorChang, TSen_US
dc.date.accessioned2014-12-08T15:25:11Z-
dc.date.available2014-12-08T15:25:11Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8838-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/17566-
dc.description.abstractThis paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18 mu m CMOS technology. When clocked at 82.58MHz, our design can easily support real-time deblocking of 2Kx1K@30Hz video application, this high performance can meet high resolution real-time application requirement.en_US
dc.language.isoen_USen_US
dc.titleAn hardware efficient deblocking filter for H.264/AVCen_US
dc.typeProceedings Paperen_US
dc.identifier.journalICCE: 2005 INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage235en_US
dc.citation.epage236en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000228036100118-
Appears in Collections:Conferences Paper