完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Cheng, CC | en_US |
dc.contributor.author | Chang, TS | en_US |
dc.date.accessioned | 2014-12-08T15:25:11Z | - |
dc.date.available | 2014-12-08T15:25:11Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-8838-0 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17566 | - |
dc.description.abstract | This paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18 mu m CMOS technology. When clocked at 82.58MHz, our design can easily support real-time deblocking of 2Kx1K@30Hz video application, this high performance can meet high resolution real-time application requirement. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An hardware efficient deblocking filter for H.264/AVC | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ICCE: 2005 INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, DIGEST OF TECHNICAL PAPERS | en_US |
dc.citation.spage | 235 | en_US |
dc.citation.epage | 236 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000228036100118 | - |
顯示於類別: | 會議論文 |