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dc.contributor.authorChin, Aen_US
dc.contributor.authorLaio, CCen_US
dc.contributor.authorChen, Cen_US
dc.contributor.authorChiang, KCen_US
dc.contributor.authorYu, DSen_US
dc.contributor.authorYoo, WJen_US
dc.contributor.authorSamudra, GSen_US
dc.contributor.authorWang, Ten_US
dc.contributor.authorHsieh, IJen_US
dc.contributor.authorMcAlister, SPen_US
dc.contributor.authorChi, CCen_US
dc.date.accessioned2014-12-08T15:25:11Z-
dc.date.available2014-12-08T15:25:11Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-9268-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/17578-
dc.description.abstractTo improve trapping using deeper well AlGaN (chi=3.8eV), lower voltage drop in high-K AlLaO(3) barrier (kappa=23), and smaller erase current by large Delta E(c) of AILaO(3)/TaN, the SiO(2)/AlGaN/AlLaO(3)/TaN devices show good 85 degrees C memory integrity of low +/- 10V 1ms P/E, large 3.9V initial Delta V(th) and 2.4V extrapolated 10-year retention. A fast 100ps P/E of +/- 11V still gives 3.0V initial Delta V(th) and 1.6V 10-year retention.en_US
dc.language.isoen_USen_US
dc.titleLow voltage high speed SiO(2)/AlGaN/AlLaO(3)/TaN memory with good retentionen_US
dc.typeProceedings Paperen_US
dc.identifier.journalIEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGESTen_US
dc.citation.spage165en_US
dc.citation.epage168en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000236225100036-
Appears in Collections:Conferences Paper