標題: 0.1 mu m poly-Si thin film transistors for system-on-panel (SoP) applications
作者: Tsui, BY
Lin, CP
Huang, CF
Xiao, YH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 mu m channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated.
URI: http://hdl.handle.net/11536/17583
ISBN: 0-7803-9268-X
期刊: IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST
起始頁: 933
結束頁: 936
Appears in Collections:Conferences Paper