標題: VPN gateways over network processors: Implementation and evaluation
作者: Lin, YN
Lin, CH
Lin, YD
Lai, YC
資訊工程學系
Department of Computer Science
公開日期: 2005
摘要: Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII IGHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.
URI: http://hdl.handle.net/11536/17644
ISBN: 0-7695-2302-1
期刊: RTAS 2005: 11th IEEE Real Time and Embedded Technology and Applications Symposium, Proceedings
起始頁: 480
結束頁: 486
顯示於類別:會議論文