完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, Chang-Tzu | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.contributor.author | Tang, Tien-Hao | en_US |
dc.contributor.author | Su, Kuan-Cheng | en_US |
dc.date.accessioned | 2014-12-08T15:25:18Z | - |
dc.date.available | 2014-12-08T15:25:18Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-2933-2 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17691 | - |
dc.description.abstract | A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49 mu mx21 mu m and consuming a very low standby leakage current of 96nA at room temperature. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Electrostatic discharge (ESD) | en_US |
dc.subject | gate leakage | en_US |
dc.subject | power-rail ESD clamp circuit | en_US |
dc.subject | silicon controlled rectifier (SCR) | en_US |
dc.title | Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | en_US |
dc.citation.spage | 21 | en_US |
dc.citation.epage | 24 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000270582500006 | - |
顯示於類別: | 會議論文 |