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dc.contributor.authorWang, Chang-Tzuen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorTang, Tien-Haoen_US
dc.contributor.authorSu, Kuan-Chengen_US
dc.date.accessioned2014-12-08T15:25:18Z-
dc.date.available2014-12-08T15:25:18Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-2933-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/17691-
dc.description.abstractA new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49 mu mx21 mu m and consuming a very low standby leakage current of 96nA at room temperature.en_US
dc.language.isoen_USen_US
dc.subjectElectrostatic discharge (ESD)en_US
dc.subjectgate leakageen_US
dc.subjectpower-rail ESD clamp circuiten_US
dc.subjectsilicon controlled rectifier (SCR)en_US
dc.titleLow-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGSen_US
dc.citation.spage21en_US
dc.citation.epage24en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000270582500006-
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