標題: | An 865-mu W H.264/AVC video decoder for mobile applications |
作者: | Liu, Tsu-Ming Lin, Ting-An Wang, Sheng-Zen Lee, Wen-Ping Hou, Kang-Cheng Yang, Jiun-Yan Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2005 |
摘要: | A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865pW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4x4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 MacroBlock/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-mu m single-poly six-metal CMOS process with area of 11.3mm(2). |
URI: | http://hdl.handle.net/11536/17722 |
ISBN: | 0-7803-9162-4 |
期刊: | 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS |
起始頁: | 301 |
結束頁: | 304 |
Appears in Collections: | Conferences Paper |