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dc.contributor.authorDe Wang, Sen_US
dc.contributor.authorChang, TYen_US
dc.contributor.authorLo, WHen_US
dc.contributor.authorLei, TFen_US
dc.date.accessioned2014-12-08T15:25:22Z-
dc.date.available2014-12-08T15:25:22Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8803-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17752-
dc.description.abstractThe On-current (I(on)) and Off-current (I(off)) instabilities of polycrystalline silicon thin-film transistors (poly-Si TFTs) were investigated under various electrical stress conditions. The stress-induced device degradation was studied by measuring the dependences of I(on) and I(off) on the drain/gate voltages. Using this technique, dissimilar variations of I(on) and I(off) after stress were observed. The differences can be attributed to the variances in the amount of charges trapped in the gate oxide and the spatial distributions of the trap states generated in the poly-Si channel. These results suggested a comprehensive model for the I(on) and I(off) instabilities of poly-Si TFTs.en_US
dc.language.isoen_USen_US
dc.subjecton-current (I(on))en_US
dc.subjectoff-current (I(off))en_US
dc.subjectinstabilitiesen_US
dc.subjectpoly-Si TFTsen_US
dc.subjectelectrical stressen_US
dc.titleMechanism of on-current and off-current instabilities under electrical stress in polycrystalline silicon thin-film transistorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 43RD ANNUALen_US
dc.citation.spage702en_US
dc.citation.epage703en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000230058000160-
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