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dc.contributor.authorHuang, WSen_US
dc.contributor.authorLin, TJen_US
dc.contributor.authorOu, SHen_US
dc.contributor.authorLiu, CWen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:25:23Z-
dc.date.available2014-12-08T15:25:23Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/17760-
dc.description.abstractThis paper presents a novel method to improve the energy awareness of the pipelined datapaths for varying throughputs. It activates the pipeline registers only when necessary; i.e. a data item can bypass the pipeline registers when the operation is free of race from the succeeding one, and when the glitch is minimal. Then, the clock pulses of the unused pipeline registers are gated to reduce the energy dissipation. Compared to the conventional clock gating approach, our proposed on-demand pipelining eliminates all redundant clock pulses whenever the peak datarate is not reached. Moreover, our method has a constant input-to-output latency for all operation modes, which significantly simplifies the integration tasks. In our simulations, the proposed on-demand pipelining saves up to 80% energy of conventional pipelined datapaths, and it can reduce about 34%-39% energy dissipation of those with gated-clock only.en_US
dc.language.isoen_USen_US
dc.titlePipelining technique for energy-aware datapathsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.citation.spage1218en_US
dc.citation.epage1221en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000232002401093-
Appears in Collections:Conferences Paper