標題: 具能量感知之資料路徑的管線化設計技巧
Pipelining Techniques for Energy-Aware Datapath Designs
作者: 林建宏
Chien-Hung Lin
任建葳
Dr. Chein-Wei Jen
電子研究所
關鍵字: 能量感知;低功率;Energy-Aware;low power
公開日期: 2002
摘要: 近年來,可攜式多媒體與通訊產品主導著消費性電子產品市場。因這些產品同時需要高性能與低功率消耗,傳統靜態式低功率設計技巧已不能滿足需求。靜態式的設計必須以最惡劣的運作環境作為設計考量,故能根據工作環境而調整功率消耗的功率(能量)感知系統日益受到重視。 為了增進資料路徑的功率感知能力,本論文提出了一個新穎的管線化設計技巧。在這個管線化設計技巧中,管線暫存器只有在需要時才會被使用。當一筆資料與下一筆資料間沒有競跑現象或管線間的脈衝雜訊不嚴重時,此筆資料會藉由直接跨越暫存器的方式到達下一級管線;被跨越而未使用的暫存器會以時脈閘門的技巧來減低功率消耗。相較於其他低功率技巧如改變供應電壓,這個管線化設計技巧能更有效且精細地利用運算間的動態特性。此外,使用我們技巧的管線化資料處理路徑並不會因工作模式的不同而改變輸入與輸出間的延遲,此特性有效地降低了系統整合上的複雜度。就實驗結果來看,相較於一般的管線化設計,我們的技巧可節省達70%的能量消耗;而與現存的時脈閘門技巧相比,我們的方法可改善15-36%的能量溢散。 此外,在3000筆運算的模擬中,我們所提出的架構會隨著所允許的運算時間拉長而降低功率消耗。因此我們開發了一個具能量感知能力的運算排序程式來最佳化我們架構的功率消耗。以DCT做模擬的結果顯示,相較於使用一般list-scheduling,利用我們的程式所得的最佳排序可節省約20%的功率消耗。
Recently, portable multimedia and wireless products dominate the consumer electronics market, which require simultaneous power and performance optimizations. The real-time computations make traditional static low power techniques less efficient, because the architecture must satisfy the worst-case performance requirements. Power (or energy) aware systems are able to scale the power dissipation with the changing conditions and quality, and thus become attractive in low power design community. This thesis presents a novel pipelining scheme to enhance the power- (or energy-) awareness of datapath designs, which activates the pipeline registers only when necessary. A datum bypasses the registers when the operation is free of race from the succeeding datum, and when the glitch is minimal, while the unused pipeline registers are clock-gated to reduce energy dissipation. The proposed scheme is able to exploit much more dynamic behaviors of an application at finer granularity of the datapath designs than other low power techniques, such as changing the supplying voltages at the run time. Moreover, our scheme has identical input-to-output latency for all operation modes, which effectively simplifies the system integration. In our simulation, the proposed scheme can reduce up to 70% energy dissipation in normal pipelines or improve 15%~36% energy of previous clock gating methods. Moreover, for identical loads, say 3,000 multiplications, the simulation result shows that the energy dissipation in our on-demand registered pipelined multiplier decreases as the allowed processing time increases. Therefore, we develop an energy-aware scheduling algorithm to optimize the energy dissipation of our multiplier. Our simulation result shows that the proposed optimal scheduling saves about 20% energy in the DCT example using list scheduling.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT910428124
http://hdl.handle.net/11536/70455
顯示於類別:畢業論文