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dc.contributor.authorLiu, TMen_US
dc.contributor.authorLee, WPen_US
dc.contributor.authorLin, TAen_US
dc.contributor.authorLee, CYen_US
dc.date.accessioned2014-12-08T15:25:23Z-
dc.date.available2014-12-08T15:25:23Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/17768-
dc.description.abstractA memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1] [2], the proposed design saves about one-half of processing cycles. With novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on H.264 system and easily achieved real-time decoding with 1080 HD (1920x1088@30fps) when working frequency is 100MHz.en_US
dc.language.isoen_USen_US
dc.titleA memory-efficient deblocking filter for H.264/AVC video codingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.citation.spage2140en_US
dc.citation.epage2143en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000232002402058-
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