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dc.contributor.authorLiu, CHen_US
dc.contributor.authorLin, TJen_US
dc.contributor.authorChao, CMen_US
dc.contributor.authorHsiao, PCen_US
dc.contributor.authorLin, LCen_US
dc.contributor.authorChen, SKen_US
dc.contributor.authorHuang, CWen_US
dc.contributor.authorLiu, CWen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:25:24Z-
dc.date.available2014-12-08T15:25:24Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/17782-
dc.description.abstractVLIW-based architectures are very popular in high-performance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.en_US
dc.language.isoen_USen_US
dc.titleHierarchical instruction encoding for VLIW digital signal processorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.citation.spage3503en_US
dc.citation.epage3506en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000232002403122-
Appears in Collections:Conferences Paper