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dc.contributor.authorYang, Hao-Ien_US
dc.contributor.authorChuang, Ching-Teen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:25:24Z-
dc.date.available2014-12-08T15:25:24Z-
dc.date.issued2009en_US
dc.identifier.isbn978-0-7695-3797-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/17803-
dc.identifier.urihttp://dx.doi.org/10.1109/MTDT.2009.25en_US
dc.description.abstractThe contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, V(T). drifts Caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of natroscale SPAM with high-kappa, metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.en_US
dc.language.isoen_USen_US
dc.titleImpacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/MTDT.2009.25en_US
dc.identifier.journal2009 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING, PROCEEDINGSen_US
dc.citation.spage27en_US
dc.citation.epage30en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000275814000005-
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