完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hsiao, TY | en_US |
dc.contributor.author | Lin, CC | en_US |
dc.contributor.author | Chang, HC | en_US |
dc.date.accessioned | 2014-12-08T15:25:25Z | - |
dc.date.available | 2014-12-08T15:25:25Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-9333-3 | en_US |
dc.identifier.issn | 1520-6130 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17818 | - |
dc.description.abstract | An application specific digital signal processor for channel coding is presented. The vector operations can improve both the performance of memory accesses and program code density. The special function units and datapaths for channel decoding accelerate the decoding speed and facilitate algorithm implementation. The processor had been fabricated in a 0.18 mu m CMOS 1P6M technology. The 2 chip size is 7.73 mm(2) including 18k bits embedded memory, and the power consumption is 141 mW while decoding Reed-Solomon code and convolutional code. In contrast with general purpose processor designs, the results show this chip has at least 50% improvement in code density and 66% data rate enhancement. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An AS-DSP for forward error correction applications | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS) | en_US |
dc.citation.spage | 609 | en_US |
dc.citation.epage | 612 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000236758900110 | - |
顯示於類別: | 會議論文 |