IEEE 802.16a 分時雙工正交分頻多重進接之上行同步技術研討與在數位訊號處理器上的實現

Abstract

正交分頻多工 (OFDM) 技術可有效地解決通訊系統中的許多問題，如多重路徑衰落、窄頻干擾等，多用戶正交分頻多工系統能依據使用者之需求將頻寬作更有效之分配。在本篇論文中，我們使用數位訊號處理器去實現分時雙工正交分頻多重進接環境下的上行同步機制。此數位訊號處理器的環境是Innovative Integration公司的Quixote個人電腦插板，其上裝置為德州儀器公司的TMS320C6416，是個擁有強大數學運算功能的處理器。

我們所處理的上行同步架構如下。上行傳輸需要作時間同步以偵測信號到達的時間，如果估測錯誤會降低間格區間 (guard interval) 用來防止多重路徑延遲造成符元間 (ISI) 干擾的能力。我們將上行同步分為兩級，第一級利用OFDM系統特有之間格區間(guard interval) 估測OFDM 符元(symbol) 大略的開始時間，此乃由於間格區間使單一符元內具有高度的自相關。第二級利用上行傳輸前置資訊 (preamble) 判斷估測OFDM 符元(symbol) 精確的開始時間。我們嘗試用兩種方式作時間同步的第二級，分別為在時間域及頻率域對收到的訊號與上行傳輸前置資訊 (preamble) 作相關性 (correlation) 分析，找到具有最大相關性的時間。

為了降低在數位訊號處理器上的運算複雜度，我們先將原始的浮點運算C程式版本修改為實數運算的程式版本，接著再考慮數位訊號處理器—TMS320C64X的特性來修改之前的程式。最後，我們在數位訊號處理器上加速了上行同步機制達374倍。

在本篇論文中，我們首先簡介分時雙工正交分頻多重進接環境下的上行同步機制。接著，我們介紹數位訊號處理器的運作環境。最後，我們描述利用數位訊號處理器的特點以加速程式的方法並且提供一些關於執行速度與同步機制效能方面的實驗結果。

OFDM is an effective transmission scheme to cope with many transmission impairments, such as multipath fading and narrowband interference. Multiuser OFDM can provide highly flexible to allocate the bandwidth according to the needs of users. In this thesis, we focus on the TDD OFDMA uplink synchronization based on IEEE 802.16a. We use digital signal processor to implement uplink synchronization schemes. The digital signal processing environment is Innovative Integration’s Quixote personal computer card, which hosts Texas Instruments’ TMS320C6416 which is a powerful signal processor with strong arithmetic operation capability.

Time synchronization is performed to detect the start time of symbols for uplink synchronization. Time synchronization errors would decrease the ability of guard interval to avoid ISI introduced by multipath channel. There are two stages in the uplink synchronization. The first stages use the guard interval to estimate the OFDM symbol start time roughly. The reason of using the guard interval is that it provides strong autocorrelation within an OFDM symbol. The second stage uses the preamble information to detect the symbol start time exactly. We present two schemes to do the second stage. One is using the correlation of received signal with preamble in the time domain and the other is in the frequency domain. The symbol start time is determined as the location with maximum correlation value.

In order to decrease the computation complexity on the DSP, we rewrite the original floating-point C programs to fixed-point version and further refine our codes by taking into account the features of the DSP chip, TMS320C6416, to produce a more efficient program. Overall, the final version for uplink synchronization schemes is 374 times faster than the original version.

In this thesis, we first introduce to the TDD OFDMA uplink synchronization schemes. Second, we describe the environment of DSP implementation. Finally, we discuss the optimization methods using the features of C64x and present experimental results on the speed and the synchronization performance.