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dc.contributor.authorLiu, TMen_US
dc.contributor.authorLee, WPen_US
dc.contributor.authorLee, CYen_US
dc.date.accessioned2014-12-08T15:25:26Z-
dc.date.available2014-12-08T15:25:26Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-9134-9en_US
dc.identifier.issn1522-4880en_US
dc.identifier.urihttp://hdl.handle.net/11536/17824-
dc.description.abstractIn this paper, we propose an area-efficient design approach to cover both in-loop and post-loop filtering processes for multiple video coding standards. In addition, we propose a hybrid filter scheduling to improve system throughput. Compared with available designs [1][2], the proposed approach saves about one-half of processing cycles, and hence reduces power dissipation. Compared to the original loop-filter, the proposed loop/post filter only incurs 20.7% of extra cost. Simulation results show that our proposal can easily achieve real-time decoding for 1080HD when the working frequency is 100MHz.en_US
dc.language.isoen_USen_US
dc.titleAn area-efficient and high-throughput de-blocking filter for multi-standard video applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 International Conference on Image Processing (ICIP), Vols 1-5en_US
dc.citation.spage3589en_US
dc.citation.epage3592en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000235773304122-
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