完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chiang, Kuen-Cheng | en_US |
dc.contributor.author | Lee, Meng-Tho | en_US |
dc.contributor.author | Shann, Jean Jyh-Jiun | en_US |
dc.contributor.author | Chung, Chung-Ping | en_US |
dc.date.accessioned | 2014-12-08T15:25:27Z | - |
dc.date.available | 2014-12-08T15:25:27Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 978-980-6560-46-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17842 | - |
dc.description.abstract | With the dramatically increasing demands for multimedia processing capabilities in portable electronic devices, the architectural supports for various multimedia computations in one platform are crucial to the success of a product. Although application-specific accelerators have performance advantages, their inflexibilities seriously impede the applicability and shorten product lifetime. On the other hand, a general-purpose processor has benefits to wide applicability but can not meet the real-time criteria in many cases. Therefore, we develop a platform consisting of a general-purpose CPU, an array of processing elements, and a shared memory to transfer data between them. In addition, we propose two scheduling methods, First-Come-First-Serve and Priority, to process the 3D models with a better performance. Experimental results indicate that the priority scheduling significantly improves the 3D-rendering in both computation speed and silicon area, compared with FCFS scheduling. Given the same speed requirements on both FCFS and priority scheduling methods, the priority scheduling requires only 75% of the silicon area. On the other hand, it yields 30% to 80% speedup with the same area. Moreover, with priority scheduling, its performance advantage can be further increased by skills such as partial reconfiguration and multi-context configuration, to reduce its reconfiguration overhead. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 3D rendering | en_US |
dc.subject | reconfigurable computing | en_US |
dc.subject | hardware scheduling | en_US |
dc.subject | processing element | en_US |
dc.subject | system-on-a-chip | en_US |
dc.title | Run-time reconfiguration scheduling of 3D-rendering on a reconfigurable system | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 3RD INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATIONS AND CONTROL TECHNOLOGIES, VOL 1, PROCEEDINGS | en_US |
dc.citation.spage | 30 | en_US |
dc.citation.epage | 35 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000243629600007 | - |
顯示於類別: | 會議論文 |