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dc.contributor.authorLin, Liang-Yuen_US
dc.contributor.authorWang, Cheng-Yehen_US
dc.contributor.authorHuang, Pao-Juien_US
dc.contributor.authorChou, Chih-Chiehen_US
dc.contributor.authorJou, Jing-Yangen_US
dc.date.accessioned2014-12-08T15:25:28Z-
dc.date.available2014-12-08T15:25:28Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8736-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17865-
dc.description.abstractNetwork-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology constructed by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overall improvement of the system throughput is 20% for 844 test cases.en_US
dc.language.isoen_USen_US
dc.titleCommunication-driven task binding for multiprocessor with latency insensitive Network-on-Chipen_US
dc.typeProceedings Paperen_US
dc.identifier.journalASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2en_US
dc.citation.spage39en_US
dc.citation.epage44en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000245021700011-
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