标题: | Architecture for area-efficient 2-D transform in H.264/AVC |
作者: | Kuo, YT Lin, TY Liu, CW Jen, CW 电子工程学系及电子研究所 Department of Electronics Engineering and Institute of Electronics |
公开日期: | 2005 |
摘要: | As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevitable in optimal designs especially when supply voltages are getting lower. However, conventional designs starting from minimization of algorithmic operations (e.g. multiply) may not always lead to optimal architectures, for the wires and the interconnection complexity significantly grow and have become predominant. This paper explores algorithms and architectures for the 2-D transform in H.264/AVC, of which the operations are very simple (i.e. only shift and add). We have shown that fewer operations do not always result in more compact designs. In our experiments with the UMC 0.18 mu m CMOS technology, the most straightforward matrix multiplication without separable 2-D operation or any fast algorithm has the best area efficiency for D1-size (720x480) video at 30fps. It saves 48%, 34% and 16% silicon area of the previous works respectively. |
URI: | http://hdl.handle.net/11536/18013 |
ISBN: | 0-7803-9331-7 |
期刊: | 2005 IEEE International Conference on Multimedia and Expo (ICME), Vols 1 and 2 |
起始页: | 1127 |
结束页: | 1130 |
显示于类别: | Conferences Paper |