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dc.contributor.authorChen, WZen_US
dc.contributor.authorLee, TLen_US
dc.contributor.authorLu, TYen_US
dc.date.accessioned2014-12-08T15:25:38Z-
dc.date.available2014-12-08T15:25:38Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8983-2en_US
dc.identifier.issn1529-2517en_US
dc.identifier.urihttp://hdl.handle.net/11536/18032-
dc.description.abstractThis paper describes the design of a 5GHz direct conversion receiver with phase and gain errors calibration for WLAN application. Integrated both LNA and mixer in a single chip, the conversion gain of the RF receiver is switch-able to compromise between linearity and noise performance. In addition, calibration schemes are proposed to compensate gain and phase errors in the I/Q signal paths. By means of this technique, the measured phase error is reduced to be less than 0.6 degrees and gain error less than 0.2 dB. The receiver provides a conversion gain of 28.2 dB in the high gain mode and 11.6 dB in the low gain mode within the signal bandwidth. The overall noise figure is 6.4dB in the high gain mode, and the third-order input intercept point (IIP3) is about -6.8dBm in the low gain mode. Implemented in a 0.18-mu m CMOS technology, it consumes 37.4 mW from a 1.8 V supply. Chip area is 1.64 mm(2).en_US
dc.language.isoen_USen_US
dc.titleA 5-GHz direct-conversion receiver with I/Q phase and gain error calibrationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papersen_US
dc.citation.spage201en_US
dc.citation.epage204en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000230541500045-
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