一個具正交相位和增益誤差校準之5GHz直接降頻射頻接收器

Abstract

近年來無線區域網路如IEEE 802.11a和HIPER LAN的發展，吸引許多相關方面研究其傳送接收器。隨著系統晶片整合的時代來到，對低成本射頻傳送接收器的需求更為強烈。而採用直接降頻架構的寬頻無線傳送接收器具有需求較少外部元件的優勢，因此能達到低成本的目標。這架構因此吸引本篇論文研究。本篇論文描述設計一個適用於無線區域網路應用之5GHz，具可變增益直接降頻接收器。而本地振盪器之頻率定為所欲接收射頻頻率之三分之二來避免功率放大器所造成的拉起現象以及本地振盪器和射頻信號接收端的交互作用。此外，還提出增益和相位誤差校準技巧來補償正交信號路徑上的不匹配情形。測量到用來評估正交誤差之鏡像排拒比為28.25分貝。射頻前端電路之轉換增益根據輸入信號功率具可切換高低來配合下一級之動態操作範圍。它可達到在高增益模式下具有轉換增益28.2分貝而在低增益模式下具有轉換增益11.6分貝。整體雜訊指收為9.4分貝而線性度為-6.8dBm(在有輸出緩衝器情況下)。籍由所提出正交校準方法，所測量到的相位誤差小於0.6度以及增益誤差小於0.2分貝。晶片面積為1.64mm2 和在1.8V的供應電壓下功率消耗37.25mW。 此外，還實現一個操作在所欲接收頻帶三分之二的頻率合成器。設計之重點主要在於最佳化相位雜訊效能，和利用所提出的具電流匹配之電荷充放器有效地降低參考信號雜頻。晶片面積為1.06mm2 以及在1.8V的供應電壓下功率消耗14.4mW。

Wireless Local Area Networks (WLANs) based on IEEE 802.11a and HIPER LAN have drawn transceiver research efforts and turn widely deployed in recent years. With the coming of soc era, a low cost RF transceiver is in strong demand. For wide band wireless transceiver direct conversion architecture is a superior candidate for fewer external required components, thus low cost design goal can be achieved. This activates the research of this work. This thesis describes the design of a 5GHz, variable gain, and direct conversion receiver for wireless LNA application. The LO frequency is set to be 2/3 of required RF frequency to avoid PA pulling and LO-RF interaction. Furthermore, gain and phase error calibration techniques are proposed to compensate mismatches in the I/Q signal path. Measured image-rejection ratio for evaluating I/Q error is about 28.2dB. The conversion gain of the RF front-end is variable to slide the available dynamic range of the following stages based on the input power level. It performs a conversion gain of 28.2 dB in the high gain mode and 11.6 dB in the low gain mode. The overall noise figure (SSB) is 9.4dB and IIP3 is about -6.8dBm (with output buffer). By means of I/Q calibration techniques, the measured phase error is less than 0.6˚ and gain error is less than 0.2 dB. It consumes chip area of 1.64mm2 and power of 37.25mW at 1.8V supply voltage. Additionally, a frequency synthesizer operating at 2/3 of required RF frequency has been implemented. The design issue is to optimize the phase noise performance and effectively reduce reference spur from mismatches by employing proposed current-match charge pump. It consumes chip area of 1.06mm2 and power of 14.4mW at 1.8V supply voltage.