標題: Formal compliance verification of interface protocols
作者: Yang, YC
Huang, JD
Yen, CC
Shih, CH
Jou, JY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: Verifying whether a building block conforms to certain interface protocol is one of the important steps while constructing an SoC However, most existing methods have their own limitations. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this paper, we propose a novel branch-and-bound algorithm for interface protocol compliance verification. The properties of the interface protocol are specified as a specification FSM, and the interface logic is formally verified at the higher FSM level. Using the FSM for property specification is relatively systematic than using other proprietary property languages, which greatly reduces the possibility of incomplete property identification. And it is shown theoretically and experimentally that the proposed algorithm can finish in reasonable time complexity.
URI: http://hdl.handle.net/11536/18036
ISBN: 0-7803-9060-1
期刊: 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers
起始頁: 12
結束頁: 15
顯示於類別:會議論文