Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cheng, CT | en_US |
dc.contributor.author | Chiao, WH | en_US |
dc.contributor.author | Shann, JJJ | en_US |
dc.contributor.author | Chung, CP | en_US |
dc.contributor.author | Chen, WF | en_US |
dc.date.accessioned | 2014-12-08T15:25:38Z | - |
dc.date.available | 2014-12-08T15:25:38Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-9060-1 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18037 | - |
dc.description.abstract | Reducing power consumption of embedded system has gained much attention recently. Reducing memory bus switchings is an effective way to reduce system power since memory bus power constitutes a great portion of the system power. While many techniques exist for reducing bus power in address buses, only a few have been proposed for content-bus power reduction. We propose a Bus-Invert and Bus-Invert with transition signaling (BIBITS) encoding scheme to reduce power consumption on instruction bus. An instruction is partitioned into fields according to its format. Four elementary Boolean functions are used as encoding functions. BIBITS uses the most suitable encoding functions for different instruction partitions. We also propose a register relabeling algorithm for BIBITS encoding to further reduce bit switchings on register fields. Simulation results show that the overall average switching reduction is 64% of unencoded bus, 59% of the previous register relabeling scheme, and 33% of Petrov's bus encoding scheme. Compared with Petrov's bus encoding scheme, our scheme uses a decoding signal table only half the size to encode all basic blocks. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | embedded system | en_US |
dc.subject | low power | en_US |
dc.subject | bus encoding | en_US |
dc.subject | BIBITS | en_US |
dc.subject | register relabeling | en_US |
dc.title | Low-power BIBITS encoding with register relabeling for instruction bus | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers | en_US |
dc.citation.spage | 41 | en_US |
dc.citation.epage | 44 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000233985300012 | - |
Appears in Collections: | Conferences Paper |