嵌入式系統低功率指令匯流排編碼方法

Abstract

近年來如何降低嵌入式系統中的耗電量已經是個非常重要的課題了。對一般的嵌入式系統而言，系統耗電有相當顯著的比例是耗費在off-chip 的匯流排上。匯流排上的耗電大約與其所傳送的資料位元變化量成正比，因此減少匯流排上的位元變化量是降低匯流排耗電的一個有效的方法。目前已經有許多減少位址匯流排耗電的研究被提出，然而減少指令匯流排耗電的編碼方法卻不多。在此，我們針對指令匯流排提出了一套編碼的方法，藉由減少指令匯流排上產生的電位變化而達成減少耗電的效果。利用application-specific 的相關資訊，於static time將hot-spots中的指令轉換成做編碼並且利用表格記錄其編碼的資訊，讓處理器能於dynamic time時做解碼。實驗結果顯示，我們的方法能夠減少指令匯流排上52%的耗電，比起Petrov提出的編碼方法約多出16％的省電效果，比起BIBIT約多出6％的省電效果。而且我們的硬體overhead與BIBITS約略相同而比Petrov的編碼方法小。整體而言，我們的研究可以帶來更好的省電效果。

Reducing the power consumption of embedded systems has gained a lot of research attention recently. In a typical embedded system, the power consumption in the off-chip buses consumes a great portion of the system power. Reducing the number of bit transitions is an effective way to reduce bus power since the bus power consumption is about proportional to the number of bit transitions. While many encoding techniques exist for reducing bus power in address buses, only a few have been proposed for instruction bus. For the low power requirement on instruction bus of embedded processors, we propose a bus encoding scheme to reduce power consumption on instruction bus. It exploits application-specific knowledge regarding program hot-spots, and identifies efficient instruction transformations to encode each instruction in hot-spots at static time. The few transformations that result in significant bit transition reductions for each hot-spot are selected by utilizing short indices stored into a table nearby the processor. The processor uses this information to efficiently restore the original bit sequence at dynamic time. The simulation results showed that our bus encoding can reduce the average power consumption of the bus by 52%, which is 16% more than Petrov’s bus encoding and 6% more than BIBITS. Moreover, the extra hardware overhead of our proposed is lower than Petrov's bus encoding and equal to BIBITS. We can conclude with certainly that our research may have more power saving opportunities.