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dc.contributor.authorWang, SHen_US
dc.contributor.authorTao, WLen_US
dc.contributor.authorWang, CNen_US
dc.contributor.authorPeng, WHen_US
dc.contributor.authorChiang, Ten_US
dc.date.accessioned2014-12-08T15:25:38Z-
dc.date.available2014-12-08T15:25:38Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-9060-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/18042-
dc.description.abstractThis paper presents an efficient hardware-software implementation with a marcoblock based pipelining and a bus interlaced architecture for all binary motion estimation (ABME), which has been proven to be simple and low cost for hardware design. The bus interleaved preprocessing module of the ABME architecture can generate downsampling and binarized data in the same flow without additional dedicated hardware. With the 3-layer binary bitplane of ABME, we use a two-dimensional (2-D) mapping unit and a binary adder tree instead of a systolic array to compute the block matching metric, which is sum of difference (SoD), in one cycle. In addition, a new bus bandwidth reduction scheme is proposed by reusing the binarized image, which can achieve up to 67% bus bandwidth saving. The experiment shows that for each macroblock, our design can finish ABME within 283 cycles with 65k gate counts synthesized by UMC 0.18 um cell library.en_US
dc.language.isoen_USen_US
dc.titlePlatform based design of all binary motion estimation (ABME) with bus interleaved architectureen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papersen_US
dc.citation.spage241en_US
dc.citation.epage244en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000233985300062-
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