一個應用於雙向預測之低功率運動估計模組設計

Abstract

本論文提出一個應用於雙向預測之低功率動量估測(motion estimation)模組設計。一個完整的動量估測模組包含整數像素動量估測、模式決定(mode decision)以及分數像素動量估測。在整數像素動量估測部份，我們使用平行二元化搜尋架構以符合低功率應用的需求。此架構能夠同時處理雙方向的動量估測；而對於P-frame搜尋，此平行二元化搜尋架構將它分割成兩個部份使得產率加倍。和傳統的搜尋架構相比，此平行二元化搜尋架構在記憶體存取、操作頻率以及硬體需求都佔有相當的優勢。在模式決定部份，本論文使用一個新的一維演算法。和原本的二維演算法相比，新演算法減少了運算延遲同時避免硬體閒置。在分數像素動量估測部份，我們採用一個低功率循序的設計。並提出整個系統平行處理架構，包含整數像素動量估測、模式決定以及分數像素動量估測。本設計需要130 cycles完成一個雙向預測的巨方塊(macroblock)搜尋。在TSMC 0.18um製程下，本設計需要131 kilo gate count及51 kilo bits的記憶體使用量。而處理每秒30張CIF大小的影像所消耗的功率為11.8 mW。和現存的設計相比，此設計所需的操作頻率最低，而在功率消耗上最多可達到34倍的改進。

This thesis proposes a low power motion estimation (ME) design for bi-directional search. A complete ME module contains integer pel ME (IME), sub-pel ME (SME) and sometimes mode decision (MD). For low power applications, our new parallel binary search architecture allows parallel processing of bi-directional search in IME. For P frame search, this parallel search architecture divides the original search into two sub-groups of partial P-frame search to double the processing throughput. Compared to conventional search architecture, this parallel binary search architecture shows advantages of lower memory access bandwidth, working frequency, and hardware design cost requirement. In MD, this work adopts a new one dimensional algorithm to reduce long latency in the original two-dimensional algorithm to avoid hardware idling. In SME, a low power sequential design solution is adopted to balance the system pipelining for IME, MD, and SME. This work completes one bi-directional macroblock search in 147 cycles with 131 kilo gate count and 51 kilo bits on-chip memory using TSMC 0.18μm technology. The power consumption for CIF 30fps is 11.8 mW. Compared to the state-of-the-art designs, this work needs the lowest working frequency and shows 34X power improvement at most.