標題: Coupling- and ECP-Aware Metal Fill for Improving Layout Uniformity in Copper CMP
作者: Co, Yu-Lun
Chen, Hung-Ming
Cheng, Yi-Kan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: With feature sizes on chips shrinking at advanced process nodes, the difficulty in manufacturability and reliability of chips is extremely increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yields. The common solution to minimize topography variation is to perform metal fills in empty spaces in the layout. However, these dummy metals will increase the capacitances between wires and then invoke delay and coupling/crosstalk noise problems. Furthermore, the impact of ECP (electroplating) should be included in the copper CMP model in order to have accurate metal fill results. In this paper, we adopt and implement an approach to considering especially the key layout parameters that affect the post-ECP topography. We further apply a greedy-based method to place the floating dummy metals in the positions with minimal additional coupling capacitances. The experimental results are encouraging. Our method not only considers the thickness range of post-ECP, it can also add much less additional coupling capacitances over a density-driven metal fill method.
URI: http://hdl.handle.net/11536/18078
ISBN: 978-1-4244-2781-9
期刊: 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM
起始頁: 122
結束頁: 125
顯示於類別:會議論文