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dc.contributor.authorWu, YCen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorChang, TCen_US
dc.contributor.authorLiu, PTen_US
dc.contributor.authorChen, CSen_US
dc.contributor.authorTu, CHen_US
dc.contributor.authorZan, HWen_US
dc.contributor.authorTai, YHen_US
dc.contributor.authorSze, SMen_US
dc.date.accessioned2014-12-08T15:25:43Z-
dc.date.available2014-12-08T15:25:43Z-
dc.date.issued2004en_US
dc.identifier.isbn0-7803-8684-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/18125-
dc.description.abstractWe have investigated the lightly-doped drain (LDD) polysilicon thin-film transistors (poly-Si TFTs) with a series of multi-channel with different widths. The ten 67 nm-wide split channels TFT has best gate control due to its tri-gate structure, and has lowest poly-Si grain boundary defects, which were passivated by NH3 plasma effectively due to its split nano-wires structure. The proposed TFT exhibits high performance electrical characteristics, such as a high ON/OFF current ratio (>10(9)), a steep subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL), suppressed kink-effect, and superior reliability.en_US
dc.language.isoen_USen_US
dc.titleHigh performance and high reliability polysilicon thin-film transistors with multiple nano-wire channelsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalIEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGESTen_US
dc.citation.spage777en_US
dc.citation.epage780en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000227158500179-
Appears in Collections:Conferences Paper