完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, YC | en_US |
dc.contributor.author | Chang, CY | en_US |
dc.contributor.author | Chang, TC | en_US |
dc.contributor.author | Liu, PT | en_US |
dc.contributor.author | Chen, CS | en_US |
dc.contributor.author | Tu, CH | en_US |
dc.contributor.author | Zan, HW | en_US |
dc.contributor.author | Tai, YH | en_US |
dc.contributor.author | Sze, SM | en_US |
dc.date.accessioned | 2014-12-08T15:25:43Z | - |
dc.date.available | 2014-12-08T15:25:43Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.isbn | 0-7803-8684-1 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18125 | - |
dc.description.abstract | We have investigated the lightly-doped drain (LDD) polysilicon thin-film transistors (poly-Si TFTs) with a series of multi-channel with different widths. The ten 67 nm-wide split channels TFT has best gate control due to its tri-gate structure, and has lowest poly-Si grain boundary defects, which were passivated by NH3 plasma effectively due to its split nano-wires structure. The proposed TFT exhibits high performance electrical characteristics, such as a high ON/OFF current ratio (>10(9)), a steep subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL), suppressed kink-effect, and superior reliability. | en_US |
dc.language.iso | en_US | en_US |
dc.title | High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | en_US |
dc.citation.spage | 777 | en_US |
dc.citation.epage | 780 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000227158500179 | - |
顯示於類別: | 會議論文 |