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dc.contributor.authorWEN, KSen_US
dc.contributor.authorWU, CYen_US
dc.date.accessioned2014-12-08T15:03:16Z-
dc.date.available2014-12-08T15:03:16Z-
dc.date.issued1995-07-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/0038-1101(94)00245-Ben_US
dc.identifier.urihttp://hdl.handle.net/11536/1823-
dc.description.abstractAn efficient and accurate 2D analysis for gate-current is proposed for short channel n-MOSFETs, in which the channel hot-electron-enhanced injection probability is proposed and expressed in terms of the actual current path and its power density flow. The accuracy of our gate-current analysis has been verified by comparisons between simulation and experimental data. This well-established gate current analysis as well as the charge boundary condition on the floating gate have been implemented into the sub-micron MOS (SUMMOS) two-dimensional device simulator for characterizing n-channel flash EEPROM writing. Comparisons with experimental EEPROM writing have been made, and quite good agreements have been obtained for test devices with different channel lengths ranging from 0.8 to 0.5 mu m for wide range of applied biases. Moreover, computer simulation for EEPROM reliability issue caused by oxide electron traps has also been performed to characterize the endurance of flash EEPROM operation.en_US
dc.language.isoen_USen_US
dc.titleA SIMPLE AND ACCURATE SIMULATION TECHNIQUE FOR FLASH EEPROM WRITING AND ITS RELIABILITY ISSUEen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/0038-1101(94)00245-Ben_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume38en_US
dc.citation.issue7en_US
dc.citation.spage1373en_US
dc.citation.epage1379en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1995RD57900015-
dc.citation.woscount1-
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