標題: A dual mode channel decoder for 3GPP2 mobile wireless communications
作者: Lin, CC
Shih, YH
Chang, HC
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2004
摘要: This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52Mb/s and 5.26Mb/s data rates respectively The memory access is reduced by the input caching scheme. And the system complexion is lowered by the efficient interleaver design. This chip is fabricated in a 0.18mum six-metal standard CMOS process, and the measured power dissipation is 83mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.
URI: http://hdl.handle.net/11536/18250
ISBN: 0-7803-8480-6
期刊: ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE
起始頁: 483
結束頁: 486
Appears in Collections:Conferences Paper