Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, HC | en_US |
dc.contributor.author | Lin, CC | en_US |
dc.contributor.author | Hsiao, TY | en_US |
dc.contributor.author | Wu, JT | en_US |
dc.contributor.author | Wang, TH | en_US |
dc.date.accessioned | 2014-12-08T15:25:57Z | - |
dc.date.available | 2014-12-08T15:25:57Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18400 | - |
dc.description.abstract | In this paper, the multi-level memory system using error control codes has been proposed. As compared with other approaches for 2(m)-level memory cells, our proposal features an effective grouping of several q-level memory cells with q > 2(m) in order to create parity bits of error control codes. Therefore, the proposed methodology can enhance both the yield and reliability without area penalty for multi-level memory systems. The BCH (72,64) code of correcting single error is presented for 5-level memory cells. In contrast to 2(2)-level memory cells, our proposal can improve yields from 61.58% to 99.92% for 16Mbit and make the mass production of 1Gbit memory practicable under the approximated model for StrataFlash(TM). Since our work was motivated from the use of q-level cells in substitution for 2(m)-level cells, not only multi-level flash memory, but also multi-level DRAM systems, can both benefit from our proposed methodology. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Multi-level memory systems using error control codes | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | en_US |
dc.citation.spage | 393 | en_US |
dc.citation.epage | 396 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000223124000099 | - |
Appears in Collections: | Conferences Paper |