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dc.contributor.authorChang, HCen_US
dc.contributor.authorLin, CCen_US
dc.contributor.authorHsiao, TYen_US
dc.contributor.authorWu, JTen_US
dc.contributor.authorWang, THen_US
dc.date.accessioned2014-12-08T15:25:57Z-
dc.date.available2014-12-08T15:25:57Z-
dc.date.issued2004en_US
dc.identifier.urihttp://hdl.handle.net/11536/18400-
dc.description.abstractIn this paper, the multi-level memory system using error control codes has been proposed. As compared with other approaches for 2(m)-level memory cells, our proposal features an effective grouping of several q-level memory cells with q > 2(m) in order to create parity bits of error control codes. Therefore, the proposed methodology can enhance both the yield and reliability without area penalty for multi-level memory systems. The BCH (72,64) code of correcting single error is presented for 5-level memory cells. In contrast to 2(2)-level memory cells, our proposal can improve yields from 61.58% to 99.92% for 16Mbit and make the mass production of 1Gbit memory practicable under the approximated model for StrataFlash(TM). Since our work was motivated from the use of q-level cells in substitution for 2(m)-level cells, not only multi-level flash memory, but also multi-level DRAM systems, can both benefit from our proposed methodology.en_US
dc.language.isoen_USen_US
dc.titleMulti-level memory systems using error control codesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGSen_US
dc.citation.spage393en_US
dc.citation.epage396en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000223124000099-
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