完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Cho, CYS | en_US |
dc.contributor.author | Chen, MJ | en_US |
dc.contributor.author | Chen, CF | en_US |
dc.date.accessioned | 2014-12-08T15:26:01Z | - |
dc.date.available | 2014-12-08T15:26:01Z | - |
dc.date.issued | 2003 | en_US |
dc.identifier.isbn | 0-7803-7653-6 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18442 | - |
dc.description.abstract | A fast and precise subthreshold slope method for extraction of gate capacitive coupling coefficient is substantially confirmed by experimental data from three types of flash memory cells: stacked gate, sidewall source-side injection (SSI), and split-gate cells. This new method furnishes promising potentials: (i) it can eliminate the effect of process variations; (ii) the traditional source or drain capacitive coupling measurement becomes unnecessary; (iii) only a few dc measurements are needed; and (iv) even dummy transistors can be removed out. Therefore, the method is highly suitable as an in-line process monitor. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Fast and precise subthreshold slope method for extracting gate capacitive coupling coefficient in flash memory cells | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ICMTS 2003: PROCEEDINGS OF THE 2003 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES | en_US |
dc.citation.spage | 186 | en_US |
dc.citation.epage | 190 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000182493300033 | - |
顯示於類別: | 會議論文 |