標題: Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells
作者: Cho, CYS
Chen, MJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: capacitive coupling;flash memory;mismatch;MOSFETs;process variations;subthreshold
公開日期: 1-七月-2004
摘要: Existing subthreshold slope methods are shown to be far from accurate in extracting gate capacitive coupling coefficient alpha(G) in stacked gate flash memory cells. The origin of the error is systematically identified: (i) process variations induced mismatch and (ii) underlying bulk capacitive coupling. To alleviate such drawbacks, a new version of the subthreshold slope method at room temperature is established: alpha(G) = 0.06(n(f) - alpha(B))/s(f), where the subthreshold swing s(f) is from flash memory cells, the subthreshold slope factor nf is from dummy transistors via threshold voltage against source-to-substrate bias measurement, and the bulk coupling coefficient alpha(B) is from a linear extension of the dimensional dependencies in the literature. The resulting alpha(G) of around 0.55 again agrees consistently with those dependencies and once drain and source coupling experiment is performed, the relation of Sigma alpha(i) approximate to 1 is achieved for all involved coupling coefficients alpha(i)'s.. The sidewall source-side injection flash memory cells are also investigated. With the improved method, this manufacturing process is proved free of process variations issue and is characterized with alpha(G) of 0.374 and fringing capacitance of 0.204 fF. (C) 2004 Elsevier Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/j.sse.2004.01.008
http://hdl.handle.net/11536/26648
ISSN: 0038-1101
DOI: 10.1016/j.sse.2004.01.008
期刊: SOLID-STATE ELECTRONICS
Volume: 48
Issue: 7
起始頁: 1189
結束頁: 1195
顯示於類別:期刊論文


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