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dc.contributor.authorCho, CYSen_US
dc.contributor.authorChen, MJen_US
dc.date.accessioned2014-12-08T15:38:55Z-
dc.date.available2014-12-08T15:38:55Z-
dc.date.issued2004-07-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.sse.2004.01.008en_US
dc.identifier.urihttp://hdl.handle.net/11536/26648-
dc.description.abstractExisting subthreshold slope methods are shown to be far from accurate in extracting gate capacitive coupling coefficient alpha(G) in stacked gate flash memory cells. The origin of the error is systematically identified: (i) process variations induced mismatch and (ii) underlying bulk capacitive coupling. To alleviate such drawbacks, a new version of the subthreshold slope method at room temperature is established: alpha(G) = 0.06(n(f) - alpha(B))/s(f), where the subthreshold swing s(f) is from flash memory cells, the subthreshold slope factor nf is from dummy transistors via threshold voltage against source-to-substrate bias measurement, and the bulk coupling coefficient alpha(B) is from a linear extension of the dimensional dependencies in the literature. The resulting alpha(G) of around 0.55 again agrees consistently with those dependencies and once drain and source coupling experiment is performed, the relation of Sigma alpha(i) approximate to 1 is achieved for all involved coupling coefficients alpha(i)'s.. The sidewall source-side injection flash memory cells are also investigated. With the improved method, this manufacturing process is proved free of process variations issue and is characterized with alpha(G) of 0.374 and fringing capacitance of 0.204 fF. (C) 2004 Elsevier Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectcapacitive couplingen_US
dc.subjectflash memoryen_US
dc.subjectmismatchen_US
dc.subjectMOSFETsen_US
dc.subjectprocess variationsen_US
dc.subjectsubthresholden_US
dc.titleImproved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cellsen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.sse.2004.01.008en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume48en_US
dc.citation.issue7en_US
dc.citation.spage1189en_US
dc.citation.epage1195en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000221174100015-
dc.citation.woscount2-
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