An efficient memory-based FFT architecture

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DC Field	Value	Language
dc.contributor.author	Chang, CK	en_US
dc.contributor.author	Hung, CP	en_US
dc.contributor.author	Chen, SG	en_US
dc.date.accessioned	2014-12-08T15:26:04Z	-
dc.date.available	2014-12-08T15:26:04Z	-
dc.date.issued	2003	en_US
dc.identifier.isbn	0-7803-7761-3	en_US
dc.identifier.uri	http://hdl.handle.net/11536/18472	-
dc.description.abstract	This paper proposes an efficient memory-based radix-2 FFT architecture, which greatly improves the memory-based FFT [5], [6] by reducing 50% memory size requirement, while maintaining a simple address generator. Specifically the memory size is reduced to 1.25N words. In addition, the multiplier utilization rate is 100%.	en_US
dc.language.iso	en_US	en_US
dc.title	An efficient memory-based FFT architecture	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS	en_US
dc.citation.spage	129	en_US
dc.citation.epage	132	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000184781400033	-
Appears in Collections:	Conferences Paper