應用於60 GHZ通信系統之高吞吐量FFT處理器設計

Abstract

FFT處理器在正交分頻多工傳輸模式之基頻接收器內是一個非常關鍵的模組。在IEEE 802.15.3c 與 IEEE 802.11ad 規格皆訂定了512點的子載波。因此我們需要一個512點的FFT架構。在單載波傳輸模式之下，FFT也廣泛地用來做有效的通道估測。 在60GHz，為了能提供Gb/s的資料傳輸速率，系統需要高吞吐量的要求，FFT的架構會碰到兩個主要的挑戰，高速和運算消耗的功率。在本文中，我們提出了一個高吞吐率、低硬體複雜度且高SQNR的FFT處理器，分別在單載波傳輸模式和正交分頻多工傳輸模式可以支援16-QAM 和64-QAM的調變方式。此FFT架構為512點八倍平行的多路徑延遲回饋 radix-2^3，利用平行及管線化方式在60GHz頻帶傳輸系統達到24 Gb/s的吞吐率。我們應用一個有效且優化的複數乘法架構避免了大量旋轉因子的存取量。動態調整SQNR技術可以大幅提高此FFT處理器的SQNR。 我們使用40 奈米 CMOS製程實現了此FFT硬體，此硬體整合在一個支援正交分頻多工傳輸模式的基頻接收器並相容於IEEE 802.15.3c 與 IEEE 802.11ad 規格。 Post-layout及晶片測量結果顯示當運行在500MHz時，FFT可以達到24Gb/s的吞吐率，功率消耗僅87mW，面積則為0.64mm^2。 在性能的測量上，SQNR可以達到73dB，MSE則為-36dB ，足以支援正交分頻多工傳輸模式規格內所訂定的最高64QAM 調變。

The FFT processor is the key component and one of the modules with high complexity in the OFDM based communication systems. In both standards (EEE 802.15.3c and IEEE 802.11ad standards), each OFDM symbol consists of 512 subcarriers; therefore, a 512-point FFT is required. The FFT operation is also widely employed in SC PHY mode for effective channel equalization. Two of the more challenging design issues associated with the FFT processor with 60GHz technology are high speed and computational power required to satisfy the stringent requirements of a high throughput demand in systems providing data rate of Gb/s. In this dissertation we present an FFT with high throughput rate, low hardware complexity and high signal to noise ratio (SQNR) for 16-QAM (SC) and 64-QAM (OFDM) modulation schemes. The proposed 512-point 8X-parallel FFT processor uses a pipelined Multipath Delay Feedback (MDF) radix-2^3 architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate of up to 24 Gb/s for 60 GHz communication systems. The proposed FFT processor also uses an area efficient optimized complex multiplier architecture that avoid the need to store the twiddle factor in memory and dynamic scaling technique to enhance the SQNR. The FFT processor has been implemented and fabricated in an OFDM mode baseband receiver system satisfying the requirements of the IEEE 802.15.3c and IEEE 802.11ad standards with a 40nm CMOS process. The post-layout results and chip measurements show that the proposed FFT processor is able to achieve a throughput rate of up to 24 Gb/s at a clock rate of 500MHz. It has a power consumption of 87mW and a core area of 0.64mm^2. The performance measurements shows that the FFT a SQNR of 73dB and MSE of -36dB to support the 64QAM modulation.