標題: A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
作者: Wu, BF
Lin, CF
電控工程研究所
Institute of Electrical and Control Engineering
公開日期: 2003
摘要: In this paper, we propose a fast pipeline VLSI architecture for ID lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511 x 2.510 mm(2), and 150 MHz, respectively.
URI: http://hdl.handle.net/11536/18473
ISBN: 0-7803-7761-3
期刊: PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS
起始頁: 732
結束頁: 735
顯示於類別:會議論文