A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

Abstract

In this paper, we propose a fast pipeline VLSI architecture for ID lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511 x 2.510 mm(2), and 150 MHz, respectively.