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dc.contributor.authorChen, HCen_US
dc.contributor.authorGuo, JIen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:26:04Z-
dc.date.available2014-12-08T15:26:04Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7761-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/18475-
dc.description.abstractThis paper presents a memory efficient design for realizing the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic computation, and exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel and then separate the kernel to be two perfect cyclic forms to facilitate an efficient realization of 1-D N-point DCT using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and N-1/2 + 1 accumulators. The comparison results with the existing designs show that the proposed design can reduce delay-area product significantly.en_US
dc.language.isoen_USen_US
dc.titleA memory efficient realization of cyclic convolution and its application to discrete cosine transformen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV: DIGITAL SIGNAL PROCESSING-COMPUTER AIDED NETWORK DESIGN-ADVANCED TECHNOLOGYen_US
dc.citation.spage33en_US
dc.citation.epage36en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000184904400009-
Appears in Collections:Conferences Paper