Design of a fully integrated high linearity dual-band CMOS LNA

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Jou, CF	en_US
dc.contributor.author	Cheng, KH	en_US
dc.contributor.author	Huang, PR	en_US
dc.contributor.author	Chen, MC	en_US
dc.date.accessioned	2014-12-08T15:26:13Z	-
dc.date.available	2014-12-08T15:26:13Z	-
dc.date.issued	2003	en_US
dc.identifier.isbn	0-7803-8163-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/18605	-
dc.description.abstract	A fully-integrated dual-band LNA (Low Noise Amplifier) with high linearity is presented in this thesis. Designed and implemented in 0.25 mu m mixed-signal CMOS process, the LNA simultaneously delivered narrow-bans gain and matching at 2.45GHz and 5.25GHz. The LNA exhibits input matching with S-11 of -20.48dB at 2.45GHz and -16.6dB at 5.25GHz. And it achieves small-signal gain of 5.78dB and 3.24dB, noise figure 4.7dB and 5.69dB, and IIP3 7dBm and 17dBm.	en_US
dc.language.iso	en_US	en_US
dc.title	Design of a fully integrated high linearity dual-band CMOS LNA	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3	en_US
dc.citation.spage	978	en_US
dc.citation.epage	981	en_US
dc.contributor.department	電信工程研究所	zh_TW
dc.contributor.department	Institute of Communications Engineering	en_US
dc.identifier.wosnumber	WOS:000221510600246	-
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