完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jou, CF | en_US |
dc.contributor.author | Huang, PR | en_US |
dc.contributor.author | Cheng, KH | en_US |
dc.date.accessioned | 2014-12-08T15:26:13Z | - |
dc.date.available | 2014-12-08T15:26:13Z | - |
dc.date.issued | 2003 | en_US |
dc.identifier.isbn | 0-7803-8163-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18607 | - |
dc.description.abstract | This paper describes the design consideration and simulation performance for a fully integrated CMOS RF front-end for 5.25 GHz application. The single chip front-end circuit consists: a 2.65dB insertion loss transmit/receive switch (T/R switch), a 13dB power gain, 2.9dB NF low noise amplifier (LNA), and a 15dBm Pout-1dB power amplifier (PA). The IC has fabricated in a TSMC 0.25-mum CMOS technology. To achieve single chip design target, this chip was designed without any off-chip matching component. The front-end circuit was designed for two operation modes: transmission mode (TX) and receiving mode (RX). We can switch two operation modes by changing the control voltage of the T/R switch. The simulation results of the TX mode has the power gain 7.27 dB and the Pout-1dB is 12 dBm. The RX mode power gain is 9.64 dB and the IIP3 is 1.1 dBm. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Design of a 0.25-mu m CMOS 5.25GHz transceiver front-end | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | en_US |
dc.citation.spage | 1090 | en_US |
dc.citation.epage | 1093 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000221510600274 | - |
顯示於類別: | 會議論文 |