完整後設資料紀錄
DC 欄位語言
dc.contributor.authorJou, CFen_US
dc.contributor.authorHuang, PRen_US
dc.contributor.authorCheng, KHen_US
dc.date.accessioned2014-12-08T15:26:13Z-
dc.date.available2014-12-08T15:26:13Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-8163-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/18607-
dc.description.abstractThis paper describes the design consideration and simulation performance for a fully integrated CMOS RF front-end for 5.25 GHz application. The single chip front-end circuit consists: a 2.65dB insertion loss transmit/receive switch (T/R switch), a 13dB power gain, 2.9dB NF low noise amplifier (LNA), and a 15dBm Pout-1dB power amplifier (PA). The IC has fabricated in a TSMC 0.25-mum CMOS technology. To achieve single chip design target, this chip was designed without any off-chip matching component. The front-end circuit was designed for two operation modes: transmission mode (TX) and receiving mode (RX). We can switch two operation modes by changing the control voltage of the T/R switch. The simulation results of the TX mode has the power gain 7.27 dB and the Pout-1dB is 12 dBm. The RX mode power gain is 9.64 dB and the IIP3 is 1.1 dBm.en_US
dc.language.isoen_USen_US
dc.titleDesign of a 0.25-mu m CMOS 5.25GHz transceiver front-enden_US
dc.typeProceedings Paperen_US
dc.identifier.journalICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3en_US
dc.citation.spage1090en_US
dc.citation.epage1093en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000221510600274-
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