Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, SH | en_US |
dc.contributor.author | Peng, WH | en_US |
dc.contributor.author | He, YW | en_US |
dc.contributor.author | Lin, GY | en_US |
dc.contributor.author | Lin, CY | en_US |
dc.contributor.author | Chang, SC | en_US |
dc.contributor.author | Wang, CN | en_US |
dc.contributor.author | Chiang, TH | en_US |
dc.date.accessioned | 2014-12-08T15:26:13Z | - |
dc.date.available | 2014-12-08T15:26:13Z | - |
dc.date.issued | 2003 | en_US |
dc.identifier.isbn | 0-7803-8185-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18610 | - |
dc.description.abstract | We present a baseline MPEG-4 AVC (Advanced Video Coding) decoder based on an optimized platform-based design methodology. With this methodology, we jointly optimize the software and hardware design of the decoder. Overall decoding throughput is increased by synchronizing the software and the dedicated co-processors. The synchronization is achieved at macroblock-level pipelining. In addition, we optimize the decoder software by enhancing the frame buffer management, boundary padding, and content aware inverse transform. To speed up motion compensation and inverse transform, which are the most computationally intensive modules, two dedicated acceleration modules are realized. For comparison, the proposed prototype decoder and MPEG-4 AVC reference decoder are evaluated on an ARM platform, which is one of most popular portable devices. Our experiments show that the throughput of the MPEG-4 reference decoder can be improved by 6 to 7 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5 frames per second (fps) for QCIF video sequences. With the dedicated accelerators, the overall throughput is increased by about 30% to reach 6.6 fps on the average and is up to 10.3 fps for slow motion video sequences. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A platform-based MPEG-4 Advanced Video Coding (AVC) decoder with block level pipelining | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ICICS-PCM 2003, VOLS 1-3, PROCEEDINGS | en_US |
dc.citation.spage | 51 | en_US |
dc.citation.epage | 55 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000222026600011 | - |
Appears in Collections: | Conferences Paper |