完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Hsu, HC | en_US |
dc.date.accessioned | 2014-12-08T15:26:14Z | - |
dc.date.available | 2014-12-08T15:26:14Z | - |
dc.date.issued | 2003 | en_US |
dc.identifier.isbn | 0-7803-8182-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18622 | - |
dc.description.abstract | A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased similar to60% by this substrate-triggered design. | en_US |
dc.language.iso | en_US | en_US |
dc.title | ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | en_US |
dc.citation.spage | 219 | en_US |
dc.citation.epage | 222 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000186384500047 | - |
顯示於類別: | 會議論文 |