完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, HC | en_US |
dc.contributor.author | Lee, ZM | en_US |
dc.contributor.author | Wu, JT | en_US |
dc.date.accessioned | 2014-12-08T15:26:15Z | - |
dc.date.available | 2014-12-08T15:26:15Z | - |
dc.date.issued | 2003 | en_US |
dc.identifier.isbn | 0-7803-7761-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18639 | - |
dc.description.abstract | A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Digital background calibration technique for pipelined analog-to-digital converters | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | en_US |
dc.citation.spage | 881 | en_US |
dc.citation.epage | 884 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000184716700221 | - |
顯示於類別: | 會議論文 |