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dc.contributor.authorLiu, HCen_US
dc.contributor.authorLee, ZMen_US
dc.contributor.authorWu, JTen_US
dc.date.accessioned2014-12-08T15:26:15Z-
dc.date.available2014-12-08T15:26:15Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7761-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/18639-
dc.description.abstractA new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.en_US
dc.language.isoen_USen_US
dc.titleDigital background calibration technique for pipelined analog-to-digital convertersen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSINGen_US
dc.citation.spage881en_US
dc.citation.epage884en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000184716700221-
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